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Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
* Explains the method and how to apply it in two practically focused chapters.
* Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
* Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
* Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
* Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
* Presents a complete derivation of the method-so you see how and why it works.
- Sales Rank: #1814421 in eBooks
- Published on: 1999-02-09
- Released on: 1999-02-09
- Format: Kindle eBook
From the Back Cover
Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.
The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.
Features
- Explains the method and how to apply it in two practically focused chapters.
- Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
- Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
- Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
- Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
- Presents a complete derivation of the method-so you see how and why it works.
About the Author
Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.
Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.
David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies.
David’s passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.
Most helpful customer reviews
0 of 1 people found the following review helpful.
Had to buy this book
By SK
I am currently doing a Masters degree in VLSI, and although this is not on the required book list, after trying endless parametric simulations of critical path device sizes, and trying to find the minimum delay, I found Logical efforts to be a much more elegant approach to doing that. Although some other books discuss it in minimal detail, there is no mention of if the same can be extended to other logic families other than Static CMOS. I went through a few pages of the book, and decide it to be a must buy. I also thought it was pretty cheap for 60$. Unfortunately, the book is pretty small - it's not like a 500 page book which I was expecting it to be.
I am yet to read through the whole book (which I plan to - very soon), and shall update this review once I am done with that. But I am expecting it to be worth the every cent I paid for it.
15 of 15 people found the following review helpful.
A very good book for designers or advanced students
By Mika Nystroem
This book is a long overdue explanation of the "Logical Effort" approach to MOS circuit design invented by two of the authors, Sutherland and Sproull, in the late 80's. The technique presented is complete and powerful, and this book should be required reading for all persons involved in high-performance or low-power MOS digital design. Nevertheless, I would not recommend it for beginners without some of what the authors call "instruction from veteran designers." The main shortcoming of the book is a lack of organization---important points are sometimes made in seemingly unrelated sections, and the sections themselves do not always appear to follow the most logical arrangement---and it could stand a more thorough editing job to clean up some of the presentation. Sometimes, I felt that information that was presented in charts would have been much more powerful in graph form. A few of the graphs in the book are misleading (arbitrary scales and unmarked breaks in scales), and some of the mathematical terminology is imprecise. The fact that the authors picked, somewhat arbitrarily, a new definition of the technology delay parameter tau (instead of sticking to the definition established by Mead & Conway in their 1980 book) is annoying. Aspiring asynchronous designers should be cautioned that the two designs for an n-input Muller C-element contrasted in Section 11.2 are logically different. A section contrasting the uses of the logical effort method in synchronous and asynchronous designs would also be welcome. All in all, however, the book is very readable, and it is easy to follow. It would be effective as a textbook, and it is a most welcome addition to my library because it treats a difficult and important topic better and in more detail than any other published work.
5 of 5 people found the following review helpful.
Blown away
By Bill Sicaras
This is without a doubt a must-have for CMOS logic and circuit designers. No doubt this will be on my desk for the forseeable future. The first two chapters present a basic introduction to the approach that is sufficient to gain a working knowledge. The remaining chapters delve into details such as applying the method to domino circuits, passgate logic, cells with unequal rise/fall times, and a complete derivation of the method. The authors are well known experts in the field of high speed circuit design, and David Harris' presentation of the material is far from bland and boring. This is one of the few technical books I had a hard time putting down. Highly recommended!
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